Loading effects on metastable parameters of CMOS latches

Author

Portmann, C.L. ; Meng, T.H.Y.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

fYear

1993

fDate

19-21 May 1993

Firstpage

21

Lastpage

22

Abstract

We have discussed the behavior of buffered and unbuffered latches versus loading from a metastable performance viewpoint. A formula to determine T/sub 0/ for a buffered latch from an unbuffered one has been described. Measured results were presented for buffered and unbuffered latches. The results shown here are relevant to standard cell or gate array ASIC designers who generally use cells contained within a library and have little control over the cells, but some control over the selection and loading. Our results show the buffered version is superior for all fanouts greater than one; however, the MTBF performance is still exponentially related to loading.

Keywords

CMOS integrated circuits; circuit reliability; flip-flops; integrated logic circuits; logic testing; stability; CMOS latches; MTBF performance; buffered latches; gate array ASIC design; loading effects; metastable parameters; standard cell design; unbuffered latches; CMOSFET logic devices; Circuit stability; Flip-flops; Integrated circuit reliability; Logic circuit fault tolerance;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on

Conference_Location

Kyoto, Japan

Type

conf

DOI

10.1109/VLSIC.1993.920520

Filename

920520