A high-speech 32 bit IEEE floating-point chip set for digital signal processing

A set of two VLSI circuits well-suited for digital signal processing is described which provides the complete 32 bit floating-point multiplier and adder functions. The data format conforms with the new IEEE P754 standard. Operations include multiplication, add, subtract, conversion to and from 24 bit integer numbers and absolute value. Multiply and add times are both 600 nsec in a flow through manner. This is reduced to 200 nsec when operated in a three stage pipeline manner using internal registers. Both chips are fabricated in high-speed NMOS with 3 micron minimum feature size, which results in low power consumption of 1.5 watts typically. They are packaged in 64-pin dual-in-line package and 68-pin leadless-chip-carrier. The applications of this chip set in FFT, digital filtering and array processing are described in this paper.