Adder-based digital signal processor architecture for 80 NS cycle time

Architecture and performance tests of a digital signal processor with the following specific features are presented: Short cycle time of 80 ns, shift & add 2´s complement arithmetic with saturation and sign-magnitude truncation operations, distributed memories with sophisticated address arithmetics, three stage pipelining, 16 bit instruction format, 20 bit internal data wordlength. In addition to standard problems sophisticated signal processing algorithms (wave digital filtering, Bergland´s real-valued FFT, etc.) can powerfully be exploited. Furthermore, this concept is well-suited for implementing multiprocessor configurations.