An efficient architecture of bitplane coding in VC-1 for real-time video processing

In this paper, we propose an efficient hardware architecture of the bitplane coding for VC-1. The bitplane coding has demerit of area, since the bitplane coding has all different 7 modes for decoding. Also, particular mode consumes many clock cycles. In order to reduce area, we use register banks that different modes share for decoding and two SRAMs that are shared for different frames. Also, we carefully designed MODE2 and DIFF module for high performance, because Differential-2 mode was the worst case. The experimental result shows that under 0.065 mum CMOS technology, the synthesized logic gate count is only 19.52K (not include two 135times40 SRAMs) when the maximum frequency is 133 MHz. Our architecture can easily support real-time processing of bitplane coding for 720p (1280times720) 30Hz video.