• DocumentCode
    3069118
  • Title

    A Low-Power Analog Sampled-llata VLSI Architecture for Equalization and FDTS/DF Detection

  • Author

    Bracken, Kimberly ; Mittal, Rohit ; Park, Joshua ; Carley, L. Richard

  • Author_Institution
    Dept. of Electrical and Computer Engineering, Carnegie Mellon University, PA
  • fYear
    1994
  • fDate
    14-17 Aug. 1994
  • Keywords
    Circuits; Computer architecture; Decision feedback equalizers; Detectors; Feedback loop; Finite impulse response filter; Intersymbol interference; Maximum likelihood detection; Signal processing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Magnetic Recording Conference 1994. Signal Processing., Digest of the
  • Conference_Location
    San Diego, CA, USA
  • Type

    conf

  • DOI
    10.1109/MRC.1994.641972
  • Filename
    641972
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3069118