3069118

A Low-Power Analog Sampled-llata VLSI Architecture for Equalization and FDTS/DF Detection

Bracken, Kimberly ; Mittal, Rohit ; Park, Joshua ; Carley, L. Richard

Dept. of Electrical and Computer Engineering, Carnegie Mellon University, PA

1994

14-17 Aug. 1994

Circuits; Computer architecture; Decision feedback equalizers; Detectors; Feedback loop; Finite impulse response filter; Intersymbol interference; Maximum likelihood detection; Signal processing; Very large scale integration;

English

ieee

Magnetic Recording Conference 1994. Signal Processing., Digest of the

San Diego, CA, USA

conf

10.1109/MRC.1994.641972

641972