Author :
Takahashi, M. ; Hamada, M. ; Nishikawa, T. ; Arakida, H. ; Tsuboi, Y. ; Fujita, T. ; Hatori, F. ; Mita, S. ; Suzuki, K. ; Chiba, A. ; Terazawa, T. ; Sano, F. ; Watanabe, Y. ; Momose, H. ; Usami, K. ; Igarashi, M. ; Ishikawa, T. ; Kanazawa, M. ; Kuroda, T.
Abstract :
This MPEG4 video codec implements essential functions in the MPEG4 committee draft. It consumes 60 mW at 30 MHz, 30% of the power dissipation of a conventional CMOS design. Measured power dissipation is summarized. 70% power reduction is achieved by low-power techniques at circuit and architectural levels. A 16b RISC processor provides software programmability. Binary shape decoding uses 20% of the computation power of the RISC processor at 30MHz clock, with negligible increase in chip power dissipation. Three-step hierarchical motion estimation reduces power dissipation.
Keywords :
decoding; large scale integration; motion estimation; reduced instruction set computing; video codecs; 30 MHz; 60 mW; MPEG4 video codec; RISC processor; architectural levels; binary shape decoding; clustered voltage scaling; computation power; low-power techniques; power dissipation; software programmability; three-step hierarchical motion estimation; variable supply-voltage scheme; Circuits; Decoding; MPEG 4 Standard; Power dissipation; Power measurement; Reduced instruction set computing; Semiconductor device measurement; Shape; Video codecs; Voltage;
