Integrating gate array design into a standard cell CAD environment

An attempt was made to integrate the present Mississippi State University (MSU) design tools with gate array design and fabrication in order to expedite prototypes. Presently, the integrated circuit designs at MSU are custom fabricated through MOSIS. These designs are generated using the Silicon Compiler Systems Generator Development Tools (SCS-GDT) and the University of California, Berkeley, Octtools LagerIV. A brief introduction of these CAD tools is presented. The CAD environment has been enhanced to provide a gate array design and fabrication path. A typical design flow for the gate array circuitry is described. The methodology produces gate array circuits by using the existing CAD tools used for standard cell design. Lasarray Corporation is the initial intended gate array vendor to fabricate these circuits