DocumentCode
3069246
Title
Subthreshold-current reduction circuits for multi-gigabit DRAM´s
Author
Sakata, T. ; Horiguchi, M. ; Itoh, K.
Author_Institution
Central Res. Lab., Hitachi Ltd., Kokubunji, Japan
fYear
1993
fDate
19-21 May 1993
Firstpage
45
Lastpage
46
Abstract
Subthreshold-current reduction, especially at room-temperature operation, is one of the key design issues in the gigabit era. Despite its importance, however, a scheme for it has not been proposed. In this paper, innovative circuits featuring a hierarchical power-line scheme and a switched-power-supply CMOS inverter with a level holder are proposed. They can drastically reduce even the active current of a 16 Gbit DRAM by one tenth, from 1.2A to 116mA.
Keywords
CMOS integrated circuits; DRAM chips; driver circuits; invertors; switched mode power supplies; 116 mA; 16 Gbit; active current reduction; hierarchical power-line scheme; level holder; multigigabit DRAM; subthreshold-current reduction circuits; switched-power-supply CMOS inverter; CMOS integrated circuits, memory; DRAM chips;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on
Conference_Location
Kyoto, Japan
Type
conf
DOI
10.1109/VLSIC.1993.920532
Filename
920532
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