Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI´s

Author

Horiguchi, M. ; Sakata, T. ; Itoh, K.

Author_Institution

Central Res. Lab., Hitachi Ltd., Kokubunji, Japan

fYear

1993

fDate

19-21 May 1993

Firstpage

47

Lastpage

48

Abstract

The reduction of exponentially increasing standby subthreshold current due to threshold-voltage (V/sub T/) scaling is one of the most important design issues for giga-scale LSIs operating at room temperature. This paper proposes a switched-source-impedance CMOS circuit featuring the subthreshold current reduction of LSIs in standby mode by 34 decades with minimum speed penalty in active mode. The circuit also features V/sub T/ variation immunity due to the negative feedback effect through the source impedance. This scheme permits battery backup even for giga-scale LSIs.

Keywords

CMOS integrated circuits; DRAM chips; VLSI; digital integrated circuits; feedback; large scale integration; switched networks; battery backup; giga-scale LSIs; negative feedback effect; room temperature; standby mode; standby subthreshold current; subthreshold current reduction; switched-source-impedance CMOS circuit; threshold voltage scaling; CMOS integrated circuits; DRAM chips; Digital integrated circuits; Large-scale integration; Switched circuits; Very-large-scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on

Conference_Location

Kyoto, Japan

Type

conf

DOI

10.1109/VLSIC.1993.920533

Filename

920533