Title :
A distributive serial multi-bit parallel test scheme for large capacity DRAMs
Author :
Sugibayashi, T. ; Takeshima, T. ; Naritake, I. ; Matano, T. ; Takada, H. ; Aimoto, Y. ; Fujita, M.
Author_Institution :
NEC Corp., Sagamihara, Japan
Abstract :
This paper describes a distributive serial multi-bit parallel test scheme suitable for large capacity DRAMs. It achieves a high parallel test bit number and, with regard to cells and sense amplifiers, the same operational margin as normal mode. Further, it imposes little restriction on test patterns. The scheme has successfully achieved a 512 bit parallel test on an experimental 256Mb DRAM.
Keywords :
DRAM chips; integrated circuit testing; 256 Mbit; distributive serial multibit parallel test scheme; dynamic RAM testing; high parallel test bit number; large capacity DRAMs; DRAM chips; Memory testing;
Conference_Titel :
VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on
Conference_Location :
Kyoto, Japan
DOI :
10.1109/VLSIC.1993.920538
