A well-synchronized sensing/equalizing method for sub-1.0 V operating advanced DRAMs

Author

Ooishi, T. ; Asakura, M. ; Tomishima, S. ; Hidaka, H. ; Arimoto, K. ; Fujishima, K.

Author_Institution

LSI Lab., Mitsubishi Electr. Corp., Itami, Japan

fYear

1993

fDate

19-21 May 1993

Firstpage

81

Lastpage

82

Abstract

In standard DRAMs, a half-V/sub cc/ bit-line (BL) precharging method is widely used because of its several advantages. However this method faces several problems as the power supply voltage Vcc becomes lower. This paper describes such problems as the MOS transistors in the sensing/equalizing circuits are affected by the body effect, fluctuation of channel length (L), and leak current. It is thefefore difficult to decide the value of the V/sub th/ which satisfies the above conditions. Accordingly, we propose a well-synchronized sensing/equalizing method that enables an ultra low-voltage operation and makes determining the V/sub th/ easy.

Keywords

CMOS integrated circuits; DRAM chips; VLSI; equalisers; synchronisation; MOS transistors; V/sub th/; advanced DRAMs; body effect; channel length fluctuation; half-V/sub cc/ bit-line precharging method; leak current; power supply voltage; sensing/equalizing circuits; sub-1.0 V; ultra low-voltage operation; well-synchronized sensing/equalizing method; CMOS integrated circuits, memory; DRAM chips; Equalizers; Synchronization; Very-large-scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on

Conference_Location

Kyoto, Japan

Type

conf

DOI

10.1109/VLSIC.1993.920547

Filename

920547