Title :
An efficient back-bias generator with hybrid pumping circuit for 1.5 V DRAMs
Author :
Tsukikawa, Y. ; Kajimoto, T. ; Okasaka, Y. ; Miyamoto, H. ; Ozaki, H.
Author_Institution :
LSI Lab., Mitsubishi Electr. Corp., Itami, Japan
Abstract :
The authors propose an efficient back-bias voltage (Vbb) generator with a newly introduced hybrid pumping circuit (HPC). This hybrid system uses one NMOS pumping transistor and one PMOS pumping transistor and can pump as low as the -Vcc level without a Vth loss. By adopting a triple-well structure at the pumping circuit area, the NMOS transistor can be employed as a pumping transistor without minority carrier injection.
Keywords :
DRAM chips; MOS integrated circuits; 1.5 V; DRAMs; NMOS pumping transistor; PMOS pumping transistor; back-bias voltage generator; hybrid pumping circuit; triple-well structure; DRAM chips; MOS integrated circuits, memory;
Conference_Titel :
VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on
Conference_Location :
Kyoto, Japan
DOI :
10.1109/VLSIC.1993.920549