A 12.5 ns 16 Mb CMOS SRAM

Author

Ishibashi, K. ; Komiyaji, K. ; Morita, S. ; Aoto, T. ; Ikeda, S. ; Asayama, K. ; Koike, A. ; Yamanaka, T. ; Hashimoto, N. ; Iida, H. ; Kojima, F. ; Motohashi, K. ; Sasaki, K.

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

fYear

1993

fDate

19-21 May 1993

Firstpage

103

Lastpage

104

Abstract

A high-speed circuit, a high-yield redundancy technique, and a soft-error immune cell are essential to realize ultra high density static RAMs. A 16 Mb (4Mx4/2Mx8) CMOS SRAM fabricated using 0.4 /spl mu/m CMOS technology is reported. An address access time of 12.5 ns is attained with 3.3 V supply voltage by using a common-centroid-geometry (CCG) layout sense amplifier and divided data bus architecture. A flexible redundancy technique (FRT) with high efficiency and with no access penalty has been incorporated into the 16 Mb SRAM. A 7.16 /spl mu/m/sup 2/ TFT load cell with stacked capacitors, achieves soft-error immunity even for the supply voltage of 3.3 V.

Keywords

CMOS integrated circuits; SRAM chips; VLSI; redundancy; 0.4 micron; 12.5 ns; 16 Mbit; 3.3 V; CMOS SRAM; TFT load cell; common-centroid-geometry layout; divided data bus architecture; flexible redundancy technique; high-speed circuit; high-yield redundancy technique; sense amplifier; soft-error immune cell; stacked capacitors; static RAMs; ultra high density memory chip; CMOS integrated circuits, memory; High-speed integrated circuits; Redundancy; SRAM chips; Very-large-scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on

Conference_Location

Kyoto, Japan

Type

conf

DOI

10.1109/VLSIC.1993.920562

Filename

920562