A 900 MHz transceiver chipset for two-way paging applications

Two bipolar analog integrated circuits are described that are used in a transceiver architecture designed for two-way paging applications. The RF front-end uses the receiver architecture to alleviate problems with conventional direct-conversion receivers. In this architecture, the input RF signal is first downconverted to an intermediate frequency of 0.2 /spl omega//sub RF/. This intermediate signal is then amplified and transferred to dc using an I/Q downconversion mixer. Quadrature signals for the I/Q mixer are generated by passing the local oscillator (LO) signal through a divide-by-four counter formed in a twisted-ring architecture. The two outputs of this counter are inherently 90/spl deg/ out-of-phase and maintain their relative phase difference over process and supply variations. Compared to a direct-conversion receiver, this architecture has several advantages. First, it has a significantly lower LO leakage since the RF filter blocks a major portion of the LO interference. Second, since signal amplification can be distributed between RF, IF and baseband, the signal level at the input of the baseband chip will be high enough to be distinguished from the 1/f noise.