Title :
A 12 bit 600 kS/s digitally self-calibrated pipeline algorithmic ADC
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
Abstract :
This paper describes an algorithmic A/D converter which employs digital error correction and self-calibration. In this paper, an approach is described that employs a nominal radix 2, 1.5 bit/stage conversion algorithm. The technique discussed in this paper can be applied to any cyclic or pipelined algorithmic converter, does not require extra clock cycles during the conversion, and no additional analog circuitry is needed. The analog circuit is extremely simple, using one operational amplifier and two latches per stage.
Keywords :
analogue-digital conversion; error correction; linear integrated circuits; pipeline processing; analog circuit; clock cycles; digital error correction; digitally self-calibrated; latches; operational amplifier; pipeline algorithmic ADC; radix 2 1.5 bit/stage conversion algorithm; Analog integrated circuits; Analog-digital conversion; Pipeline processing; Radix conversion;
Conference_Titel :
VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on
Conference_Location :
Kyoto, Japan
DOI :
10.1109/VLSIC.1993.920571