A low-voltage low-power 13-b pipelined switched-current cyclic A/D converter

The switched-current circuit has received extended research on communication data conversion due to its current steering and low power. This paper presents a high speed, high resolution, and low-power CMOS switched-current cyclic analog-to-digital converter (ADC). The high performance is attributed to the use of the following components: (1) a high-performance residual amplifier which takes two clock cycles to double a current; and (2) an efficient cyclic RSD algorithm which provides 1.5 b resolution without using two matched reference currents; (3) the fine-tuned pipeline structure to increase the conversion speed. Results are based on the previous results of Wang, et al. [1999] which implied the pipelined structure can increase the conversion speed up to 10 M Samples/sec on 2 μm process and the power will only increase 6 fold compared to the non-pipelined structure