Title :
Research and Design of Low Power Consumption Testing Generator for Integrated Circuits
Author_Institution :
Coll. of Phys. & Electron. Sci., Guizhou Normal Univ., Guiyang, China
Abstract :
In this paper, Sources of power consumption for CMOS logical circuits are analyzed and several BIST technologies of low power consumption are summarized. In order to reduce the switching activity rate of internal nodes in circuit-under-test and raise the correlation between testing vector, the Random Single Input Change (RSIC)test theory is introduced. It can reduce the switching activity rate of nodes in the circuit-under-test to realize low power consumption during testing without lossing fault coverage, especially suitable for BIST of digital VLSI.
Keywords :
CMOS digital integrated circuits; CMOS logic circuits; VLSI; built-in self test; power consumption; BIST technologies; CMOS logical circuits; circuit-under-test; digital VLSI; integrated circuits; power consumption; power consumption testing generator; random single input change test theory; testing vector; Built-in self-test; CMOS logic circuits; CMOS technology; Circuit analysis; Circuit testing; Energy consumption; Integrated circuit technology; Integrated circuit testing; Power generation; Switching circuits; Built-in-self-test; Integrated Circuit Testing; Low Power Consumption Testing; Testing Vector Generator; Vector Leap;
Conference_Titel :
Information and Computing (ICIC), 2010 Third International Conference on
Conference_Location :
Wuxi, Jiang Su
Print_ISBN :
978-1-4244-7081-5
Electronic_ISBN :
978-1-4244-7082-2
DOI :
10.1109/ICIC.2010.357
