• DocumentCode
    3072246
  • Title

    On the Semantics of Scenario-Based Specification Based on Timed Computational Tree Logic

  • Author

    Wenrui Li ; Pengcheng Zhang

  • Author_Institution
    Sch. of Math. & Inf. Technol., Nanjing Xiaozhuang Univ., Nanjing, China
  • fYear
    2013
  • fDate
    4-7 June 2013
  • Firstpage
    1
  • Lastpage
    10
  • Abstract
    Scenario-based specifications have been widely used to specify the behavior of reactive systems in a visual and intuitive way. Timed Property Sequence Chart (TPSC) is a recently proposed scenario-based specification for specifying timing properties for real-time systems. However, there is currently no model checking tool available to verify timing properties specified by TPSC specifications. To mitigate this gap, this paper provides the semantics rules for TPSC by explicitly translating TPSC into Timed Computational Tree Logic (TCTL) that is a real time temporal logic. Two kinds of rules are defined: basic and compositional rules. Basic rules discuss how to translate a single message in a TPSC specification into a TCTL formula, while compositional rules show how to compose these basic TCTL formulas according to compositional operators. The classification of basic and compositional rules makes our translations more efficient. The translation process is illustrated by a case study. The translating correctness is also proved by the practical measurement of real-time specification patterns. The work described here opens an indirect way to model checking real-time requirements represented in TPSC specifications by translating TPSC specifications into TCTL formulas.
  • Keywords
    formal specification; temporal logic; TPSC specification; basic rule; compositional operator; compositional rule; real-time system; scenario-based specification; temporal logic; timed computational tree logic; timed property sequence chart; timing property; Clocks; Model checking; Real-time systems; Semantics; Software; Syntactics; Timing; Scenario-based specifications; Timed Computational Tree Logic; Timed Property Sequence Chart; Timing Properties;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Software Engineering Conference (ASWEC), 2013 22nd Australian
  • Conference_Location
    Melbourne, VIC
  • ISSN
    1530-0803
  • Type

    conf

  • DOI
    10.1109/ASWEC.2013.11
  • Filename
    6601287