Title :
A Strategy for Interconnect Testing in Stacked Mesh Network-on-Chip
Author :
Chan, Min-Ju ; Hsu, Chun-Lung
Author_Institution :
Dept. of Electr. Eng., Nat. Dong Hwa Univ., Hualien, Taiwan
Abstract :
3D IC process has be a tendency in recent years. But the progress of IC process technologies recently has the related problems. In the 3D NoC architecture, the 3D IC process makes the placement and routing to become more complex. Then, the faults increase because of the more complex architecture. Therefore, we have to study a methodology to solve the problem. At present, the testing approach for NoC interconnect fault is based on the 2D architecture. The 3D simulated tool is not perfect. Therefore, we have to study a feasible method to test 3D architecture. In this paper, we consider how will apply a mature interconnect test approach for the 2D NoC architecture to test the 3D NoC architecture. Then, we are able to achieve the objective for increasing the yield of product through the replacement of defective chips.
Keywords :
integrated circuit interconnections; integrated circuit testing; network-on-chip; 3D IC process; 3D NoC architecture; NoC interconnect fault; interconnect testing; stacked mesh network-on-chip; Built-in self-test; Circuit faults; Integrated circuit interconnections; Three dimensional displays; Wires; built-in self-test (BIST); interconnect testing; network-on-chip (NoC);
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems (DFT), 2010 IEEE 25th International Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4244-8447-8
DOI :
10.1109/DFT.2010.21
