Title :
High-Performance Cluster-Fault Tolerance Scheme for Hybrid Nanoelectronic Memories
Author :
Haron, Nor Zaidi ; Hamdioui, Said
Author_Institution :
Comput. Eng. Lab., Delft Univ. of Technol., Delft, Netherlands
Abstract :
Error correction codes (ECCs) are common industrial practices for tolerating intermittent and transient faults in semiconductor memories. They have been also proposed for emerging hybrid nanoelectronic memories. However, this solution comes at higher cost in terms of performance penalty and area overhead. This paper proposes a high performance cluster-fault correction scheme for hybrid nanoelectronic memories. The scheme, referred to as Double Three-Residue Code (D3R), is based on combining the advantages of N-tuple Modular Redundancy (NMR) and Redundant Residue Number System (RRNS). Experimental results show that D3R decodes 10 to 28 times faster as compared to RRNS variants and Reed-Solomon (RS) while achieving similar cluster-fault correction capability.
Keywords :
decoding; digital storage; error correction codes; fault tolerance; nanoelectronics; redundancy; D3R decoding; N-tuple modular redundancy; area overhead; cluster-fault tolerance scheme; double three-residue code; error correction codes; hybrid nanoelectronic memories; performance penalty; redundant residue number system; Circuit faults; Converters; Decoding; Fault tolerant systems; Nuclear magnetic resonance; Redundancy; N-tuple modular redundancy; fault tolerance; hybrid nanoelectronic memories; redundant residue number system;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems (DFT), 2010 IEEE 25th International Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4244-8447-8
DOI :
10.1109/DFT.2010.24
