SEU-Hardened Dual Data Rate Flip-Flop Using C-Elements

Aggressive device scaling has reduced the gate capacitance, which resulted in increasing sensitivity to radiation induced soft errors. In addition, technology scaling has reached to the point of maximum clock frequency to maintain acceptable energy consumption. On the other hand, technology advancements are demanding higher throughput and data rates. To mitigate these problems, we propose a unique single event upset (SEU) hardened dual data rate (DDR) flip-flop using c-elements, “Firebird”. Unlike the existing rad-hard flip-flops, the proposed Firebird design not only is truly protected to SEUs, but it also latches in both rising and falling edges of the clock for DDR operation. With the use of DDR, the clock frequency (activity) can be reduced by 2x with no impact on performance. In comparison with the simplified Built-in Soft Error Resilient Flip-Flop (B-SER-FF) with DDR at 45 nm CMOS process, the proposed Firebird design consumes 19.6% less power, with 9.5% high C2Q delay. The power-delay product of the proposed Firebird design is 11.2% better than its counterpart, B-SER-FF with DDR.