DocumentCode :
3072569
Title :
Hardware Efficient Algorithm for Complex Arithmetic
Author :
Khare, Kavita ; Khare, Nilay ; Aggarwal, Supriya
Author_Institution :
Dept. of Electron. & Commun. Eng., M.A.N.I.T., Bhopal
fYear :
2009
fDate :
6-7 March 2009
Firstpage :
209
Lastpage :
213
Abstract :
There has been high demand for low power and area efficient implementation of complex arithmetic operations in many digital signal processing applications. The CORDIC (coordinate rotation digital computer) algorithm is a unique technique for performing various complex arithmetic functions using shift-add iterations. This paper proposes an enhanced version of new CORDIC algorithm (obtained from conventional CORDIC by using Taylor series expansion of sine and cosine functions) discussed in. The recursive architecture implementation of the revised new CORDIC algorithm improves the throughput by 50% as compared to the previous design. Revised algorithm, VLSI implementation of the design and its performance comparison with are discussed.
Keywords :
VLSI; digital arithmetic; signal processing; CORDIC; Taylor series expansion; VLSI implementation; complex arithmetic operations; coordinate rotation digital computer algorithm; digital signal processing applications; hardware efficient algorithm; recursive architecture implementation; sine-cosine functions; Algorithm design and analysis; Application software; Computer architecture; Digital arithmetic; Digital signal processing; Hardware; Signal processing algorithms; Taylor series; Throughput; Very large scale integration; CORDIC; FPGA; ISE Simulator; Recursive Architecture; Xilinx9.2i;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advance Computing Conference, 2009. IACC 2009. IEEE International
Conference_Location :
Patiala
Print_ISBN :
978-1-4244-2927-1
Electronic_ISBN :
978-1-4244-2928-8
Type :
conf
DOI :
10.1109/IADCC.2009.4809008
Filename :
4809008
Link To Document :
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