Title :
A New Soft-Error Resilient Voltage-Mode Quaternary Latch
Author :
Rhod, Eduardo ; Sterpone, Luca ; Carro, Luigi
Author_Institution :
Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
Abstract :
Multiple-valued logic circuits represent nowadays a new technology challenge to realize integrated circuits using less silicon area and having low power and high frequencies characteristics. Above this technology, quaternary logic is increasingly attractive for Field Programmable Gate array devices, where the costs of area, power and interconnections delay play a key role in the overall circuit costs. These characteristics make quaternary logic circuits appealing for space applications where area and power reduction are extremely desired. In order to enable multiple-value logic for space applications it is necessary to evaluate and harden this technology against radiation effects inducing soft-errors. In this paper, we firstly propose a characterization of a voltage-mode quaternary latch in the presence of induced transients that vary in intensity, local and time of transient injection as well as the value of the input stimulus. Secondly, we present a new architecture of the latch circuit in order to allow the detection and correction of any radiation-induced effect. Detailed experimental analysis demonstrated the radiation sensitivity to transient effects of classical and hardened quaternary logic latch. Results demonstrated that the proposed design results fully robust to soft error with respect to the standard design.
Keywords :
field programmable gate arrays; multivalued logic circuits; radiation effects; space vehicle electronics; area reduction; field programmable gate array devices; integrated circuits; latch circuit; multiple-value logic; multiple-valued logic circuits; power reduction; quaternary logic circuits; radiation effects; radiation-induced effect; soft-error resilient voltage-mode quaternary latch; space applications; Adaptation model; Integrated circuit modeling; Inverters; Latches; Logic gates; Transient analysis; Transistors;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems (DFT), 2010 IEEE 25th International Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4244-8447-8
DOI :
10.1109/DFT.2010.31