An FPGA based Walsh Hadamard transforms

The Walsh-Hadamard transforms are important in many image processing applications including compression, filtering and code design. This paper presents a novel architecture for the fast Hadamard transform, using distributed arithmetic techniques. The mathematical model for the algorithm proposed, the associated design using both a distributed arithmetic ROM and accumulator structure and a sparse matrix factorisation technique, together with the implementation of the algorithm on a Xilinx FPGA board are described. The design has O(2n) computation time complexity, where n is the input data wordlength, requires less area when compared with existing systolic architectures and is suitable for FPGA implementations