DocumentCode
3072736
Title
A 220 mm/sup 2/ 4 and 8 bank 256 Mb SDRAM with single-sided stitched WL architecture
Author
Kirihata, T. ; Gall, M. ; Hosokawa, K. ; Dortu, J.-M. ; Wong, H. ; Pfefferl, K.-P. ; Ji, B. ; Weinfurtner, O. ; DeBrosse, J. ; Terletzki, H. ; Selz, M. ; Ellis, W. ; Wordeman, M. ; Kiehl, O.
fYear
1998
fDate
5-7 Feb. 1998
Firstpage
78
Lastpage
79
Abstract
A 220 mm/sup 2/ 256 Mb SDRAM uses (1) single-sided stitched-wordline architecture, (2) a shared-row decoder with asymmetric block activation, (3) an intra-unit address increment pipeline scheme, (4) single-ended read-write drive (RWD), and (5) selectable row domain and divided column redundancy.
Keywords
DRAM chips; decoding; memory architecture; pipeline processing; redundancy; 256 Mbit; SDRAM; asymmetric block activation; divided column redundancy; intra-unit address increment pipeline scheme; selectable row domain; shared-row decoder; single-ended read-write drive; single-sided stitched WL architecture; wordline architecture; Adders; CMOS technology; Circuit faults; Decoding; Fuses; Mirrors; Pipelines; Random access memory; Redundancy; SDRAM;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-4344-1
Type
conf
DOI
10.1109/ISSCC.1998.672383
Filename
672383
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