Single Event Induced Double Node Upset Tolerant Latch

This paper presents a construction of a single-event-induced-double-node-upset-tolerant latch. The proposed latch does not tolerate upsets caused by single- and double-node-transients which single-events rarely induce because of single-event-transient occurrence mechanism. This paper also shows an evaluation result indicating the area of the proposed latch is only 0.44 times that of the conventional multiple-node-upset-tolerant latch, which tolerate any double-node-upsets and some limited triple-node-upsets, and is 1.01 times as large as that of the single-node-upset-tolerant latch DICE.