Efficient recursive implementation of multiplierless FIR filters

The efficient implementation of selective multiplierless digital FIR filter is very desired solution for low-power consumption applications. Filter requirements such as sharp transition and large stop-band attenuation require very high filter order and usually large power consumption. The solution of this problem can be to use predefined hardware filter structures with small number of operations per input sample in spite of the very high filter order. In this paper we provide a systematic approach for solving the problem using computer algebra system (CAS). The methodology is based on (1) sketching the filter structure that is known to have excellent properties appropriate as embedded solution, (2) automated building the knowledge into CAS in a form of the schematic description, (3) automated derivation of filter properties such as transfer functions or implementation codes, (4) defining a strategy for combining intermediate results, and (5) plotting the frequency responses in order to verify the final solution.