DocumentCode
3073167
Title
A sub-0.1 /spl mu/m circuit design with substrate-over-biasing [CMOS logic]
Author
Oowaki, Y. ; Noguchi, M. ; Takagi, S. ; Takashima, D. ; Ono, M. ; Matsunaga, Y. ; Sunouchi, K. ; Kawaguchiya, H. ; Matsuda, S. ; Kamoshida, M. ; Fuse, T. ; Watanabe, S. ; Toriumi, A. ; Manabe, S. ; Hojo, A.
Author_Institution
Adv. Semicond. Device Lab., Toshiba Corp., Kawasaki, Japan
fYear
1998
fDate
5-7 Feb. 1998
Firstpage
88
Lastpage
89
Abstract
A substrate-over-biasing technique together with gate-substrate tie circuitry continues the downward trend of gate delay and reduces power for sub-0.1 /spl mu/m LSIs.
Keywords
CMOS logic circuits; VLSI; delays; integrated circuit design; logic gates; CMOS logic; LSIs; gate delay; gate-substrate tie circuitry; power reduction; substrate-over-biasing; Circuit synthesis; Circuit testing; Delay; Fuses; Laboratories; Large scale integration; Leakage current; Semiconductor devices; Substrates; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-4344-1
Type
conf
DOI
10.1109/ISSCC.1998.672387
Filename
672387
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