New gate oxide wear-out model for accurate device lifetime projections on vertical drain NMOSFET

Author

Pae, S. ; Agostinelli, M. ; Curello, G. ; Lau, S. ; Ramey, S. ; Alavi, M.

Author_Institution

Technol. Dev. Q&R, Intel Corp., Hillsboro, OR, USA

fYear

2004

fDate

18-21 Oct. 2004

Firstpage

19

Lastpage

22

Abstract

In this paper, the reliability of the vertical drain NMOS (VDNMOS) device structure has been evaluated for a state of the art CMOS process. In past technologies, reliability was restricted by hot carrier degradation effects. With technology scaling, gate oxide wear-out has become the reliability limiter. A new VDNMOS oxide wear-out model has been developed and verified with low voltage stress data. This new model accurately captures the dependence of VDNMOS lifetime on drain to gate bias and can be used to better project the maximum drain voltage at operating condition.

Keywords

MOSFET; hot carriers; semiconductor device models; semiconductor device reliability; CMOS process; VDNMOS reliability; device lifetime projection; drain/gate bias lifetime dependence; gate oxide wear-out model; hot carrier degradation effect; low voltage stress data; maximum operating drain voltage; technology scaling; vertical drain NMOSFET; Breakdown voltage; CMOS process; CMOS technology; Degradation; Hot carriers; Low voltage; MOS devices; MOSFET circuits; Semiconductor device modeling; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report, 2004 IEEE International

Print_ISBN

0-7803-8517-9

Type

conf

DOI

10.1109/IRWS.2004.1422730

Filename

1422730