DocumentCode :
3073304
Title :
Minimum-adder integer multipliers using carry-save adders
Author :
Gustafsson, Oscar ; Ohlsson, Henrik ; Wanhammar, Arid Lars
Author_Institution :
Dept. of Electr. Eng., Linkoping Univ., Sweden
Volume :
2
fYear :
2001
fDate :
6-9 May 2001
Firstpage :
709
Abstract :
In this paper we investigate graph-based minimum-adder integer multipliers using carry-save adders. The previously proposed approaches use carry-propagation adders with two inputs and one output and are not suitable for carry-save adder implementation when we have a single input and a carry-save output of the multiplier. Using carry-save adders avoids carry propagation and results in a higher throughput. We find that mapping from carry-propagation adders to carry-save adders is suboptimal and the multipliers should be designed for carry-save adders directly. Multiplier graphs of up to five adders are presented. Exhaustive search finds that for carry-save adders savings are possible for coefficients with wordlength larger than nine bits. For 19 bits an average saving of over 10% is obtained
Keywords :
adders; carry logic; graph theory; logic circuits; multiplying circuits; carry-save adders; graph-based integer multipliers; minimum-adder integer multipliers; throughput improvement; Adders; Arithmetic; Costs; Digital signal processing; Finite impulse response filter; Hardware; Propagation delay; Signal processing algorithms; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
Type :
conf
DOI :
10.1109/ISCAS.2001.921169
Filename :
921169
Link To Document :
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