Impact of buried layer processing on gate oxide integrity [CMOS processing]

Author

O´Connell, Barry ; Yang, Robert ; Yindeepol, Wipawan ; De Santis, Joseph ; Strachan, Andy ; Coppock, William ; Foote, Richard ; Dark, Charles ; Sethna, Prochy ; Chaparala, Prdsad

Author_Institution

Nat. Semicond. Corp., Santa Clara, CA, USA

fYear

2004

fDate

18-21 Oct. 2004

Firstpage

23

Lastpage

27

Abstract

Buried layers are used in bipolar devices to lower collector resistance in bulk silicon and SOI (silicon-on-insulator) technologies. They are also used with deep trench for isolating different devices types. This work investigates the effect of buried layer processing on CMOS capacitor reliability, comparing results between bulk silicon and SOI substrates. Opposing results from bulk and SOI technologies indicate different degradation mechanisms at play. The SOI starting material requires that metal contaminant gettering be taken in to account in the processing of the buried layers.

Keywords

CMOS integrated circuits; buried layers; isolation technology; leakage currents; silicon-on-insulator; CMOS capacitor reliability; CMOS processing; MOS channel leakage; SOI; SOI substrates; bulk silicon substrates; buried layer processing; deep trench isolation; degradation mechanisms; gate oxide integrity; metal contaminant gettering; silicon-on-insulator; Boron; CMOS process; CMOS technology; Capacitors; Degradation; Gettering; Isolation technology; Semiconductor diodes; Silicon on insulator technology; Surface contamination;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report, 2004 IEEE International

Print_ISBN

0-7803-8517-9

Type

conf

DOI

10.1109/IRWS.2004.1422731

Filename

1422731