Fast wafer level data acquisition for reliability characterization of sub-100 nm CMOS technologies

Author

Kerber, A. ; Kerber, M.

Author_Institution

Infineon Technol. AG, Munich, Germany

fYear

2004

fDate

18-21 Oct. 2004

Firstpage

41

Lastpage

45

Abstract

The application of fast measurement techniques for the reliability assessment of sub-100 nm CMOS technologies was recently proposed in the literature. To realize fast wafer level current measurements, ranging from nA to mA, a measurement setup was developed consisting of an analog input/output PCI card and (log-lin) current-voltage converters. With this setup, a measurement time resolution of ∼20 μs was achieved, which is significantly faster than the conventional source measurement unit (SMU) based measurements via GPIB control. The setup was verified using time dependent dielectric breakdown measurements (of n-MOSFETs) on SiON gate dielectrics and charge trapping measurements in HfO₂ layers.

Keywords

CMOS integrated circuits; MOSFET; convertors; dielectric thin films; electric current measurement; semiconductor device breakdown; semiconductor device measurement; semiconductor device reliability; 100 nm; CMOS technology reliability characterization; HfO₂; MOSFET; SMU; SiON; analog input/output PCI card; charge trapping measurements; current-voltage converters; fast wafer level data acquisition; gate dielectrics; measurement time resolution; source measurement unit; time dependent dielectric breakdown measurements; wafer level current measurements; CMOS technology; Charge measurement; Current measurement; Data acquisition; Dielectric breakdown; Dielectric measurements; MOSFET circuits; Measurement techniques; Measurement units; Time measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report, 2004 IEEE International

Print_ISBN

0-7803-8517-9

Type

conf

DOI

10.1109/IRWS.2004.1422736

Filename

1422736