• DocumentCode
    3073646
  • Title

    A study on the 3DIC interconnection using thermal compression bond with non conductive paste process

  • Author

    Mu-Hsuan Chan ; Huei-Nuan Huang ; Chien-Feng Chan ; Chun-Tang Lin ; Yang, Ming-Hsuan ; Jeng Yuan Lai

  • Author_Institution
    Siliconware Precision Ind. Co., Ltd., Taichung, Taiwan
  • fYear
    2012
  • fDate
    24-26 Oct. 2012
  • Firstpage
    274
  • Lastpage
    276
  • Abstract
    Three dimensional (3D) stacking technology has been purposed to meet miniaturization trend, high performance, and multi-function electronic products. Chip stacking with through silicon via (TSV) and high density lead free interconnection are believed to realize 3D stacking package. Due to the narrow dispensing request for multi-chip connection, non-conductive paste (NCP) is one of the solutions to replace capillary underfill. Nevertheless, voidless control and wettability are two critical challenges for large dies size flip chip ball grid array (FCBGA) 3D package. In this paper, fine pitch u-bump for large die size 3D stacking using thermal compression bonding (TCB) with NCP is demonstrated. In order to achieve voidless, bonding parameter was studies in different pre-heat time. The effect of bonding conditions such as force, temperature, and time on wettability has been performed. The results showed that longer pre-heat time could accomplish voidless. The u-bump wettability exhibited relationship between TCB parameters and characteristics of NCP. Finally, reliability test was tested for NCP properties discussion.
  • Keywords
    ball grid arrays; flip-chip devices; integrated circuit bonding; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; wetting; 3D stacking package; 3DIC interconnection; FCBGA 3D package; NCP; TCB; TSV; capillary underfill; chip stacking; fine pitch u-bump; flip chip ball grid array; high density lead free interconnection; multichip connection; multifunction electronic product; nonconductive paste process; reliability test; thermal compression bonding; three dimensional stacking technology; through silicon via; u-bump wettability; voidless control; Bonding; Flip chip; Force; Integrated circuit interconnections; Reliability; Stacking; Vehicles;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2012 7th International
  • Conference_Location
    Taipei
  • ISSN
    2150-5934
  • Print_ISBN
    978-1-4673-1635-4
  • Electronic_ISBN
    2150-5934
  • Type

    conf

  • DOI
    10.1109/IMPACT.2012.6420264
  • Filename
    6420264