New hole trapping characterization during NBTI in 65 nm node technology with distinct nitridation processing [MOSFETs]

Author

Denais, M. ; Bravaix, A. ; Huard, V. ; Parthasarathy, C. ; Bidaud, M. ; Ribes, G. ; Barge, D. ; Vishnubhotla, L. ; Tavel, B. ; Rey-Tauriac, Y. ; Perrier, F. ; Revil, N. ; Arnaud, F. ; Stolk, P.

Author_Institution

STMicroelectronics, Crolles, France

fYear

2004

fDate

18-21 Oct. 2004

Firstpage

121

Lastpage

124

Abstract

We have developed in this work a new characterization methodology which includes stressing and measurement in a single experimental step. This overcomes the influence of the hole detrapping effect in ultra-thin gate-oxides (T_OX=1.4-1.6 nm) and enables comparison of gate-oxide nitridation impacts on negative bias temperature instability (NBTI). This new approach offers possibilities to measure the whole degradation and to improve DC NBTI characterization in operating logic circuits.

Keywords

MOSFET; hole traps; nitridation; semiconductor device measurement; thermal stability; 1.4 to 1.6 nm; 65 nm; DC NBTI characterization; MOSFET; N; NBTI degradation; SiO₂-Si; combined stressing/measurement; gate-oxide nitridation NBTI effects; hole trapping/detrapping characterization; logic circuits; negative bias temperature instability; plasma nitridation; ultra-thin gate-oxides; CMOS technology; Capacitance-voltage characteristics; Current measurement; Degradation; MOSFETs; Niobium compounds; Nitrogen; Oxidation; Stress measurement; Titanium compounds;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report, 2004 IEEE International

Print_ISBN

0-7803-8517-9

Type

conf

DOI

10.1109/IRWS.2004.1422753

Filename

1422753