A case study on exploration of last-level cache for energy reduction in DDR3 DRAM

This paper studies the effects of last-level cache on DRAM energy consumption. In particular, we explore how different last-level cache configurations affect the idle periods of DRAM, and whether those idle periods can be exploited through the use of self refresh power down mode to enable maximum energy reduction in both the energy consumption of the last-level cache and DRAM. A suitable last-level cache configuration reduces active power consumption of DRAM by reducing read/write accesses to it and use of the self refresh power down mode reduces background power of DRAM, creating a possibility of significant energy reduction. We propose a power mode controller to adaptively transition DRAM to self refresh power down mode when a memory request hits the last-level cache, and activate the DRAM when a memory request misses the last-level cache. We experimented with eight applications from mediabench, and found that an optimal last-level cache configuration with self refresh power down mode can save up to 89% energy compared to a standard memory controller. Additionally, the use of self refresh power down mode degraded the performance by a maximum of 2% only. Thus, we conclude that exploration and optimization of last-level cache can result in significant energy savings for memory subsystem with little performance degradation.