A Real-Time Interactive Verification System for ASIC Design

The verification takes over 70% of the whole workload in design of digital chips, especially the chips for communications. Practically, the FPGA verification is common used because the simulation verification is low-efficient. But it is not a perfect substitute for the simulation verification. So the method to improve the efficiency of the simulation should be investigated. The verification system proposed in this paper has been used in the verification work of the chips of the Dual-system navigation receiverpsilas baseband circuit. The verification methods in the system reduce the debug time, which are separating the part of the verification process to avoid the repetition and providing the real-time interactive interface to the designer.