Title :
Gate oxide integrity improvement by optimising poly deposition process
Author :
Ng, Tze Kiong ; Yap, Andrew ; Lo, Keng Foo ; Ang, Poh Chuan
Author_Institution :
Chartered Semicond. Manuf. Ltd., Singapore, Singapore
Abstract :
The gate oxide integrity of oxide thickness 13.5 nm has been studied for different amorphous poly deposition conditions. The poly grain was varied by the poly deposition conditions. The study, which was carried out on BiCMOS devices, showed substantial reliability degradation in the gate oxides when using amorphous poly deposition at temperatures of 550 °C versus 530 °C and thickness of 60 nm versus 65 nm. A possible mechanism for the drastic reliability degradation is the protrusion of poly grains into the softening oxide at high temperature.
Keywords :
crystal microstructure; dielectric thin films; leakage currents; semiconductor device breakdown; semiconductor device reliability; 13.5 nm; 530 degC; 550 degC; 60 nm; 65 nm; BiCMOS devices; amorphous poly deposition process optimisation; deposition temperatures; dielectric breakdown; gate leakage current; gate oxide integrity; gate oxide reliability degradation; oxide high temperature softening; oxide thickness; poly grain oxide protrusion; poly grain variation; post process effects; reliability failure mechanism; Amorphous materials; Circuit testing; Current measurement; Dielectrics; Electronic equipment testing; Gate leakage; Leakage current; Manufacturing processes; Substrates; Voltage;
Conference_Titel :
Integrated Reliability Workshop Final Report, 2004 IEEE International
Print_ISBN :
0-7803-8517-9
DOI :
10.1109/IRWS.2004.1422760
