Logic Gate Failure Characterization for Nanoelectronic EDA Tools

As semiconductor process geometries shrink to nanometer regime, the transistors and interconnects become exceedingly susceptible to failure due to their physical limitations. Implementing a resilient circuit using imperfect nanoelectronic devices, such as Carbon Nanotube Field Effect Transistors (CNFETs), requires a detailed failure-based design optimization and cell characterization integrated into the Electronic Design Automation (EDA) tools. The focus of this paper is to provide a basic method of cell failure characterization for failure-based design optimization in nanoelectronic EDA tools. In a typical CNFET process, it is shown that the failure probability of a 1× NAND and 1× NOR gates are about twice and three times the failure probability of a 1× Inverter, respectively. EDA tools have to perform detailed "failure analysis" to identify "failure-prone critical paths" for further optimization, similar to critical path optimization during timing analysis.