DocumentCode
3073968
Title
DRAM standby current failure: the influence of hot carrier degradation on voltage level-up shifter circuit
Author
Lee, K.J. ; Seo, J.Y. ; Jung, J.W. ; Jung, G.J. ; Lee, J.H. ; Hwang, S.J. ; Yoon, C.K.
Author_Institution
Memory Div., Samsung Electron., Gyeonggi-Do, South Korea
fYear
2004
fDate
18-21 Oct. 2004
Firstpage
173
Lastpage
174
Abstract
In this report, the phenomenon of standby state current failure of dynamic random access memory (DRAM), which incorporates a low voltage to high voltage CMOS level-up shifter, was investigated. As a result, DRAM standby current failure due to on/off time delay of the level shifter circuit has been identified as being responsible for n-MOSFET ON-state current decrease by hot carrier injection (HCI).
Keywords
CMOS memory circuits; DRAM chips; hot carriers; integrated circuit reliability; CMOS level-up shifter; DRAM; HCI; hot carrier degradation; hot carrier injection; level shifter on/off time delay; n-MOSFET ON-state current decrease; standby state current failure; voltage level-up shifter circuit; Circuit simulation; Circuit testing; Degradation; Delay effects; Hot carriers; Low voltage; MOSFET circuits; Photoelectricity; Random access memory; Temperature dependence;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Reliability Workshop Final Report, 2004 IEEE International
Print_ISBN
0-7803-8517-9
Type
conf
DOI
10.1109/IRWS.2004.1422767
Filename
1422767
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