Reconfigurable Processor Architecture For High Speed Applications

Revolutions in the domain of computing have molded the structures and characteristics of computing systems. Conventional computing techniques involved the use of application specific integrated circuits to achieve a high performance at the cost of extremely inflexible hardware design meanwhile the flexibility of hardware design was achieved at the cost of slow speed processing by using programmable processors. The emergence of reconfigurable computing has filled the gap between the flexibility and performance of system. Reconfigurable computing combines the high speed of application specific integrated circuits with the flexibility of the programmable processors. The reconfigurable processors have further boosted up the dramatic nature of reconfigurable computing systems. These processors configure the most optimal and efficient hardware resources according to the demands of running application. The configured hardware resources can be modified or reconfigured later on according to the new demands of the running application. In this research paper reconfigurable processor architecture has been presented for high speed applications. The proposed reconfigurable processor is based on very long instruction word architecture. The proposed processor is using an efficient multi-threaded configuration controller and a multi-ported configuration memory to configure the multiple reconfigurable function units concurrently with minimum possible configuration overhead.