Embedded systems for safety-critical and mixed-criticality applications

Summary form only given. Multi-core processors promise a number of benefits for development of dependable embedded systems. They offer higher performance than single-core processors and consume less energy than high-speed single cores of equivalent computational power, reducing this way a number of computational nodes and wiring in a system and increasing the system robustness. Moreover, the cores of the heterogeneous multi-core processors can be tailored to match the specific functionalities of the embedded computer system. Despite these promises, multi-cores are not automatically well-suited for safety-critical and mixed-criticality embedded systems. If not carefully designed, the lack of adequate spatial and temporal partitioning and the barely analyzable worst-case timing behavior of their performance-enhancing features render the validation of claims about the dependability and correct timing behavior of applications on today´s powerful multicores to be impossible. Therefore, this tutorial discusses the key architectural principles that must be followed when constructing embedded multi-core systems for safety-critical and mixed-criticality applications. Moreover, it introduces and discusses a new design methodology suitable for the implementation of such applications on the top of the multi-core systems that follow these principles.