Hypervisor-Based Virtual Hardware for Fault Tolerance in COTS Processors Targeting Space Applications

Commercial off the shelf processors are becoming mandatory in space applications to satisfy the ever-growing demand for on-board computing power. As a result, architecture able to withstand the harshness of the space environment are needed to cope with the errors that may affect such processors, which are not specifically designed for being used in space. Beside design and implementation costs, validation of the obtained architecture is a very cost- and time-consuming operation. In this paper we propose an architecture to quickly develop dependable embedded systems using time redundancy. The main novelty of the approach lies in the usage of a hyper visor for implementing seamlessly time redundancy, consistency checking, temporal and spatial segregation of programs that are needed to guarantee a safe execution of the application software. The proposed architecture needs to be validated only once then, provided that the same hyper visor is available for different hardware platforms, it can be deployed without the need for re-validation. We describe a prototypical implementation of the approach and we provide experimental data that assess the effectiveness of the approach.