Title :
A Design of Self-Defect-Compensatable Hardware Neuron for Multi-layer Neural Networks
Author :
Yamamori, Kunihito ; Tashiro, Keisuke ; Kusano, Masamichi ; Yoshihara, Ikuo
Author_Institution :
Fac. of Eng., Univ. of Miyazaki, Miyazaki, Japan
Abstract :
Neural network has a problem that learning time becomes so long for real world problems. To achieve fast learning, some researchers proposed to implement a neural network into Wafer Scale Integration (WSI). Since WSI uses one wafer as a parallel computer, a part of defect leads entire system fault. Therefore a defect compensation method is necessary to implement a neural network into WSI. Partial Retraining (PR) method has proposed as one of the defect compensation methods for neural network. However PR method is not verified whether it will perform well on digital hardware or not. It is also not clear how much is circuit required. In this paper we report a design of self-defect-compensatable neuron with PR method by VHDL, and evaluate it by simulations.
Keywords :
hardware description languages; multilayers; neural nets; VHDL; WSI; defect compensation method; multilayer neural network; partial retraining method; self-defect-compensatable hardware neuron; wafer scale integration; Artificial neural networks; Equations; Hardware; Mathematical model; Multi-layer neural network; Neurons; Training; Defect compensation; Field programmable gate array; Neural network; Partial retraining scheme; VHDL;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems (DFT), 2010 IEEE 25th International Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4244-8447-8
DOI :
10.1109/DFT.2010.17
