A VLSI parallel machine for speech recognition

An integrated circuit used as a basic cell of a systolic array for speech recognition is described. An array of hundred such chips can support real-time recognition of utterances for a vocabulary containing up to 1800 words. The recognition algorithm is based on Bahl and Jelinek stochastic modeling of the errors made during the phonetic analysis of speech. The chip has been designed using 5 microns NMOS technology, and contains 12,000 transistors. We successively present the algorithm, the organization of the array, the internal architecture of the chip, and finally, the expected performances of the machine.