Probabilistic Modeling of Frequent Value Bus Encoding Scheme for Low Power Computation

Exponential increase in scale of integration, is increasing day by day and movement of high volume information among various parts of computing system contributes a lot on overall power budget. Feasibility of system depends on power consumption in modern computing systems. There are various ways to reduce power requirement. Dynamic power requirement is the dominating factor among them. Power consumption due to communication on system-level buses contributes a lot of power consumption. Scheme used to reduce dynamic power in called as bus encoding technique. Various schemes have been proposed in literature to encode data to reduce the number of bus transition. Data volume of information that belongs to computer system is not always used with equal probability, but frequencies of usages are different and high for only few sets of data. Bus encoding scheme suggested with the above fact is called as frequent value encoding (FVE) scheme. This paper provides mathematical model of FVE scheme. Paper aims at providing a framework for evaluation of bus encoding algorithms for 8 to 64-bit information flowing in computing system. Probabilistic model has been drawn and result shows efficiency of FVE scheme.