Memory access pattern-aware DRAM performance model for multi-core systems

The DRAM latency modeling is complex because most chips contain row-buffers and multiple banks to exploit patterns of DRAM accesses. As a result, the latency of DRAM access not only depends on the circuit timing parameters but also memory access patterns. This study derives an analytical model that predicts the DRAM access performance using DRAM timing and memory access pattern parameters. As a performance metric, the bank busy time of DRAM is used. The pattern parameters employed represent memory access characteristics such as the number of row-buffer misses, the number of read or write requests that hit the row-buffers, etc. The proposed model not only relates the DRAM access performance with the memory access pattern but also provides information for timing optimization of next generation DRAMs. The model is evaluated with SPLASH-2 benchmark by using cycle-accurate timing simulations with DDR3 timings. The evaluation results show that, in memory-bounded cases, the execution time is limited by bank utilization, not by the data bus occupation ratio.