Compact Designs of SubBytes and MixColumn for AES

The most critical factors responsible for bottleneck in the design and implementation of high-speed AES (Advanced Encryption Standard) architectures for any resource constrained target platform such as an FPGA are Substitute byte/Inverse SubstituteByte and MixColumn/InverseMixcolumn operations. Most implementations conventionally make use of the memory intensive look up table approach for Substitute byte/Inverse SubstituteByte (SB/ISR) block implementations resulting in an unbreakable delay. The proposed work employs a memory-less combinatorial design for the implementation of SB/ISR as an alternative to achieve higher speeds by eliminating memory access delays while retaining or enhancing the over all area efficiency. The work also explores use of sub-pipelining to further enhance the speed and throughput of the suggested implementation. The architecture employs optimization in both inverter design and isomorphic mapping using composite field arithmetic to reduce the area requirements. The proposed design replicates the very compact SB/ISR reported in [6] and [13] with an overall reduction in area requirement of 18% and 14% resply. The Optimum construction of composite field for AES S-Box are selected based on the complexities of subfield operations in the design of inverter in GF (2⁸) for the effects of irreducible polynomial coefficients, and isomorphic mappings to minimize gate count and critical path. This decreased size of SB/ISR design could help for an area limited hardware implementations and also to allow more copies of SB/ISR for parallelism and/or pipelining of AES. The proposed decomposition method for integrated MixColumn/InverseMixcolumn (MC/IMC) optimizes the area and path delay.