Majority logic decoding in type-I hybrid-ARQ protocols

Side information provided by sets of orthogonal check sums in a majority logic decoder for block codes is used in a type-I hybrid ARQ (automatic repeat request) error control scheme. The side information is obtained through a simple modification of the majority logic decoder. It is shown that the reliability performance of Reed-Muller and other majority logic decodable codes can be substantially improved at the expense of a very small reduction in throughput. For raw channel bit error rates up to 10^-2, the reliability of the modified decoder is many orders of magnitude greater than that of the unmodified decoder. The simplicity of the decoding circuit permits implementation in systems with very high data rates