Title :
A 400 M sample/s 6b CMOS folding and interpolating ADC
Author :
Flynn, M. ; Sheahan, B.
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
Abstract :
A 6b 400 MSample/s folding and interpolating CMOS ADC uses a low-impedance current-mode approach. Current division interpolation in the folders allows fast low-voltage operation. This interpolation together with a short aperture comparator, gives good performance for high-frequency inputs, without using a sample-and-hold. The ADC uses a single clock and its complement. The 0.6 mm/sup 2/ CMOS converter, fabricated in a 0.5 /spl mu/m BiCMOS process dissipates 200 mW from a 3.2 V supply.
Keywords :
CMOS integrated circuits; 0.5 micron; 200 mW; 3.2 V; 6 bit; BiCMOS process; CMOS; current division interpolation; folding ADC; high-frequency inputs; interpolating ADC; low-impedance current-mode approach; low-voltage operation; short aperture comparator; single clock; Circuits; Drives; Frequency; Impedance; Interpolation; Latches; Metastasis; Power dissipation; Resistors; Transconductance;
Conference_Titel :
Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4344-1
DOI :
10.1109/ISSCC.1998.672412
