Optimization of a piezoelectric crystal driver stage using system simulations

Using SPICE, successful efforts have previously been made in modeling piezoelectric devices and their functionality. In this paper the piezoelectric device is simulated together with MOS transistor models. The design of a CMOS piezoelectric crystal driver stage is presented. Measurements on a manufactured chip verify the chosen design approach and the performance predicted by the simulations. In the work, achieving small silicon area while maintaining maximum possible output ultrasound pulse amplitude has been a key criterion. The driver stage has been implemented using a 0.6 μm CMOS process. Measurements and simulations have been performed using PZ-27 crystals without backing. Results clearly show that the performance of a complete system comprising both piezoelectric and electronical devices can be predicted with good accuracy using the proposed SPICE simulation approach